1. Field of the Invention
The invention relates to prefetching data, and more particularly to an apparatus and method for prefetching data in a bus system.
2. Description of the Related Art
The Advanced High-Performance Bus (AHB) protocol, is a bus protocol introduced within the Advanced Microcontroller Bus Architecture (AMBA), which has the following features of: burst transfers, split transactions, non-tristate implementation, several bus Masters, large bus-widths (64/128 bit) and single-cycle bus master handover. According to the features, AHB can be implemented in a high-performance and high-clock-frequency system. AHB comprises three parts: a Master, a Slave and a Infrastructure part, wherein data transfer within the AHB is issued by the Master and responded by the Slave.
FIG. 1 shows a timing diagram of the signals within a conventional AHB system. As shown in FIG. 1, the signal M_HTRANS is a control signal provided by the Master to indicate to the transmission type of a data transfer, which comprises: Idle, Busy, Sequential and Non-sequential data transfer transmission types. The signal M_HADDR is an address signal provided by the Master, and the signal M_HRDATA is the data received by the Master. The signal S_HADDR is an address signal received by the Slave, and the signal S_HRDATA is the read data response from the Slave. In time period T1, the Master issues the signal M_HTRANS to indicate that the transmission type is Non-sequential, i.e. the current transferring address and control signals are unrelated to the last transferring address and control signals. In addition, the Master issues the address signal M_HADDR and the control signal M_HWRITE to read the data of address A0. Next, in time period T2, the Master issues the signals to read the data of address A1. The Slave receives the address signal A0 in time period T2, and responds by sending the data D0 of the address A0 to the Master in time period T4, and then the Master receives the data D0 in time period T5. Next, the slave receives the address signal A1 in time period T6 and responds by sending the data D1 to the Master in time period T7, and then the Master receives the data D1 in time period T8. In a conventional AHB system, the Master issues the signals in time period T1 to request to read the data of the address A0 and receives the responded data D0 in time period T5, wherein the time interval between time periods T1 and T4 is 4 time periods. Furthermore, the Master issues the signals in time period T2 to request to read the data of the address A1 and receives the responded data D1 in time period T8, which further requires 6 time periods. Therefore, improvement in data transfer speed of an AHB bus system is desired.